What this article covers - What HBM is, and precisely how it differs from conventional DRAM - How the technology has evolved across four generations, from HBM1 to HBM4 - Which companies are involved at each stage of production - Which Korean firms are drawing the most attention - The risk factors every investor must understand before acting

What is HBM? A motorway analogy

The easiest way to understand High Bandwidth Memory is through a road analogy. Conventional DRAM resembles a narrow country lane: no matter how fast individual vehicles (data packets) travel, a road with few lanes will inevitably congest. HBM is the equivalent of widening that road into a motorway with dozens of lanes. Rather than pushing clock speeds ever higher, HBM dramatically increases the interface width — the number of lanes — so that far more data can move simultaneously.

Two core technologies make this possible. The first is vertical stacking. Instead of laying DRAM chips side by side on a flat surface, HBM stacks multiple dies on top of one another, like floors in an apartment block. This packs more memory into the same footprint and brings it physically closer to the processor. The second is Through-Silicon Via (TSV) technology — effectively the lifts connecting those floors. Microscopic holes are drilled through each chip and filled with conductive material, allowing the stacked dies to exchange data directly in the vertical direction.

The resulting HBM module sits directly alongside the GPU or AI accelerator it serves, rather than being plugged into a distant slot on the motherboard. That short, wide data pathway is what makes all the difference in AI workloads.

Why HBM matters now

Training and running large language models (LLMs) is not merely a question of raw computational speed. These models contain hundreds of billions of parameters that must be fetched continuously from memory. However fast the arithmetic units inside a GPU may be, they sit idle if the data they need cannot be delivered quickly enough. The industry calls this the memory bottleneck.

HBM exists to eliminate that bottleneck. For years, the AI chip performance race was about building faster processors; it has now shifted to a contest over how rapidly data can be fed to those processors. A single high-end Nvidia AI accelerator carries multiple stacks of HBM, and the bandwidth and capacity of that memory increasingly determines the chip's real-world performance.

Four generations of HBM

Since the standard was first ratified by the industry body JEDEC in 2013, each generation of HBM has widened the metaphorical motorway and improved the efficiency of its lifts.

Generation | Standard adopted | Interface width | Bandwidth per stack | Key characteristics

HBM1 | 2013 | 1,024-bit | — | First commercial HBM; developed by SK Hynix

HBM2 | 2016 | 1,024-bit | — | Higher capacity and speed

HBM2E | 2020 | 1,024-bit | ~460 GB/s | Deployed in early AI accelerators such as Nvidia's A100

HBM3 | 2022 | 1,024-bit | up to 819 GB/s | Channels doubled from 8 to 16; HBM enters the mainstream

HBM3E | 2023 | 1,024-bit | >1.2 TB/s | Current volume product; used in Nvidia's Blackwell generation

HBM4 | Standard due 2025 | 2,048-bit (doubled) | ~2 TB/s (standard); up to 3.3 TB/s per stack (Samsung single-stack) | Base die manufactured on advanced foundry process for the first time; strategies diverge by company

The most significant step in this table is the jump to HBM4. From HBM2 through HBM3E, each generation essentially kept the same 1,024-bit road width and focused on moving traffic faster. HBM4 doubles the road itself to 2,048 bits and increases the number of channels from 16 to 32. This is not an incremental improvement; it is a structural redesign.

Capacity is also scaling up. HBM3E can stack up to 16 DRAM dies to achieve 48 GB per module; HBM4 is designed to reach 64 GB in the same 16-die configuration. Power efficiency is expected to improve by roughly 40% compared with HBM3E. The trajectory is unambiguous: more capacity, greater bandwidth, lower power consumption.

Nor does the roadmap end at HBM4. Korea's Hanmi Semiconductor has announced it is already developing equipment with HBM5 and HBM6 production in mind — a clear signal that the technology's evolution is far from over. Industry analysts expect HBM5 to deliver bandwidth of around 4 TB/s per stack.

Who makes HBM, and how — a supply chain map

A single HBM module passes through multiple layers of companies before it reaches an AI server. Understanding this chain explains why the universe of potential beneficiaries extends well beyond any single name.

① The three memory makers — where the core product is built

Only three companies in the world produce HBM: SK Hynix, Samsung Electronics, and the American firm Micron Technology. SK Hynix pioneered the technology in 2013 and has maintained a leadership position in the market ever since. Samsung, the dominant force in memory broadly, is pursuing it closely. Micron has been gaining share rapidly, having secured supply agreements for its HBM3E chips in Nvidia's Blackwell GPUs.

The most consequential difference between the three lies in their relationship with advanced chip manufacturing — a point addressed below.

② Foundries — where the HBM "base" is fabricated

Starting with HBM4, a meaningful architectural change alters the competitive landscape. The bottommost die in an HBM stack — known as the base die, which manages power delivery and signal control — must now be manufactured using an advanced logic foundry process rather than a conventional DRAM process. Mirae Asset Securities estimates that this base die accounts for roughly 15% of total HBM4 production costs, a share large enough to matter strategically.

The three memory makers have responded with markedly different approaches. SK Hynix has outsourced base die production to TSMC, Taiwan's dominant contract chipmaker, reasoning that leveraging TSMC's advanced logic process will deliver superior performance even at the cost of external dependence. Samsung has taken the opposite path, manufacturing the base die internally using its own 4-nanometre foundry process — a vertically integrated strategy made possible by the fact that Samsung is the world's only company that combines leading-edge memory, foundry, logic design, and packaging under one roof. This internal collaboration, known in the industry as Design-Technology Co-Optimisation (DTCO), is a potential structural advantage. That said, Samsung's foundry division has ceded considerable market share to TSMC in recent years, and some analysts regard HBM4 as a critical test of whether Samsung can demonstrate its foundry capabilities are competitive once more. Micron, prioritising cost, chose to fabricate the base die on its own DRAM process — a decision that reportedly made it harder to meet Nvidia's performance requirements, leaving Micron somewhat behind in the supply race.

The broader implication is that HBM4 marks a shift from a contest over how many DRAM dies can be stacked to a contest over how sophisticated the base die can be. Memory competitiveness and foundry competitiveness are becoming inseparable. TSMC, meanwhile, benefits from both sides: it is producing base dies for SK Hynix and portions of Micron's requirements, cementing its position as an indispensable node in the HBM supply chain.

③ Back-end equipment — bonding the stack together

Stacking dozens of DRAM dies does not, by itself, create a functional HBM module. Each die must be precisely bonded to the next using heat and pressure in a process carried out by a Thermo-Compression Bonder (TC Bonder). Korea's Hanmi Semiconductor holds an estimated 71% share of this equipment market. Its HBM4-capable TC Bonders are already in mass-production use, and the company is developing a next-generation "wide TC Bonder" designed for HBM5 and HBM6.

However, as stack heights rise beyond 16 dies, a newer technique called hybrid bonding — in which chips are fused directly without the adhesive bumps used in conventional bonding — becomes increasingly important. In this area, established international equipment makers such as Applied Materials, Besi, and ASMPT hold longstanding patents and a head start. Hanmi Semiconductor is building a dedicated facility and accumulating its own hybrid bonding intellectual property to compete, while domestic rival Hanwha Semitec has also entered the race.

④ Substrates and materials — the bridge between HBM and GPU

Integrating HBM and a GPU onto a single package requires high-precision substrate technology. FC-BGA (Flip-Chip Ball Grid Array) substrates, which allow multiple chips to be mounted on a single large board, are critical to advanced AI semiconductor packaging. Korean firms Isu Petasys (high layer-count substrates for AI servers) and Daeduck Electronics (FC-BGA) are prominent participants in this segment. They do not make HBM itself, but no HBM package can function without their components.

⑤ Outsourced assembly and test (OSAT) — packaging and inspection specialists

Large foundries such as TSMC and Samsung often subcontract packaging and testing work to specialist firms known as OSATs (Outsourced Semiconductor Assembly and Test providers). In Korea, Hana Micron operates in this space. Precision test equipment for detecting defects in finely stacked chips is another niche: Lino Industrial holds a significant share of that market.

The HBM value chain at a glance

① Memory makers (core HBM production) SK Hynix · Samsung · Micron ↓ ② Foundries (base die fabrication — strategies differ by company) Samsung (in-house, 4nm) · TSMC (for SK Hynix and portions of Micron) ↓ ③ Back-end equipment (die bonding) Hanmi Semiconductor (TC Bonder) · Hanwha Semitec ↓ ④ Substrates and materials (package interconnects) Isu Petasys · Daeduck Electronics ↓ ⑤ Assembly, packaging, and test Hana Micron · Lino Industrial ↓ ⑥ End application (completed AI accelerator) Nvidia · AMD · others

Seeing the chain laid out in this way makes clear why "SK Hynix is the only HBM beneficiary" is too narrow a view. At least five distinct layers of companies contribute to every HBM module that reaches an AI server. Because the competitive dynamics and technological barriers differ at each layer, an investor's choice of where in the chain to invest materially changes the risk and return profile of the position.

Risk factors every investor should weigh

Any honest assessment of HBM must acknowledge its risks alongside its opportunities.

The memory cycle has not been abolished. The semiconductor memory industry has always been subject to sharp price swings driven by the balance between supply and demand. AI-driven demand has altered the amplitude of recent cycles, but it has not eliminated them. Extrapolating today's boom conditions indefinitely is a dangerous assumption.

Competitive positions shift with each technology generation. A company that leads today is not guaranteed to lead tomorrow. The emerging contest over hybrid bonding — where overseas incumbents hold significant advantages — illustrates how each technology transition invites fresh challengers. Dominant market positions in this industry are provisional, not permanent.

Different rungs of the supply chain carry different risk profiles. The capital intensity, margin structure, and cyclical sensitivity of a company that invests tens of billions in fabrication facilities differ fundamentally from those of a specialist equipment maker serving a single niche. Grouping every "HBM-related stock" under one label and evaluating them by the same criteria is an imprecise approach that is likely to mislead.

*Further reading: how HBM is priced and why it is valued so differently from commodity DRAM — a natural next step for readers who want to deepen their understanding of the economics behind the technology.*